Programmable Device Circuits and Systems

Uday Panwar ¹, Kavita Khare ¹

Affiliations
1 Department of Electronics and Communication Engineering, MANIT, Bhopal, IN

Abstract

High leakage current in Deep-Sub Micron (DSM) regimes is becoming a significant contributor to power dissipation of CMOS circuit parameters are reduced. This paper focusing on the leakage current which is highly dependent on potential applied on the transistors gate. That's why it can be said that input of the logic gate is able to control the leakage of the gate appropriately during run time of the device. Consider the input vector methodology to analyse NAND logic with 2 inputs using HSPICE simulator with BPTM technologies (i.e. 180nm, 130nm, 90nm, 65nm, 45nm) model. It gives the similar behaviour of leakage current with every technology models. Hench we can shift the logic gate input with its Minimum Leakage Vector (MLV) during run time of the device. Above technique is process parameter independent and there is no need of any extra power supply to reducing the leakage.

Keywords

Leakage Current, MLV, Input Vector Control.

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Nidhi Thakur ¹, Kavita Khare ²

Affiliations
1 Electronics & Communication Engineering Department, T.I.T. College, Bhopal, IN
2 Electronics & Communication Engineering Department, MANIT, Bhopal, IN

Abstract

This paper presents design of ring oscillator based voltage controlled oscillator for wide frequency range applications requiring on-chip oscillators to generate clocks at low power. The structure and operating principle of ring oscillator have been described and the expression for the frequency of oscillation of a CMOS delay cell based conventional ring oscillator is presented. The VCO is designed and simulated in 45nm CMOS technology with BSIM 4.3.0 MOSFET model, level 54 parameters using SPICE simulator. At constant supply voltage (VDD) of 1V, as input control voltage varies from 0.3V to 1V in a step of 0.2V the output frequency changes from 0.54GHz to 4.5GHz, thus providing a maximum tuning range of 88%. The total power dissipation is of the order of 60 μW, with center drain current of 60.0 μA for current mirror formed with MOSFETs M3 & M4. The Phase Noise obtained for the proposed design is 0.116mV/Hz1/2 at 1MHz.

Keywords

Voltage Controlled Oscillator (VCO), Tuning Range, Phase Noise, CMOS Inverter, Power Dissipation.

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